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  <body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h1 class="register-section">MSMON_CSU, MPAM Cache Storage Usage Monitor Register</h1><p>The MSMON_CSU characteristics are:</p><h2>Purpose</h2>
        <p>Accesses the CSU monitor instance selected by <a href="ext-msmon_cfg_mon_sel.html">MSMON_CFG_MON_SEL</a>.</p>

      
        <p>MSMON_CSU_s is a Secure cache storage usage monitor instance selected by the Secure instance of <a href="ext-msmon_cfg_mon_sel.html">MSMON_CFG_MON_SEL</a>.
MSMON_CSU_ns is a Non-secure cache storage usage monitor instance selected by the Non-secure instance of <a href="ext-msmon_cfg_mon_sel.html">MSMON_CFG_MON_SEL</a>.
MSMON_CSU_rt is a Root cache storage usage monitor instance selected by the Root instance of <a href="ext-msmon_cfg_mon_sel.html">MSMON_CFG_MON_SEL</a>.
MSMON_CSU_rl is a Realm cache storage usage monitor instance selected by the Realm instance of <a href="ext-msmon_cfg_mon_sel.html">MSMON_CFG_MON_SEL</a>.</p>

      
        <p>If <a href="ext-mpamf_idr.html">MPAMF_IDR</a>.HAS_RIS is 1, the monitor instance accessed is for the resource instance currently selected by <a href="ext-msmon_cfg_mon_sel.html">MSMON_CFG_MON_SEL</a>.RIS and the monitor instance of that resource instance selected by <a href="ext-msmon_cfg_mon_sel.html">MSMON_CFG_MON_SEL</a>.MON_SEL.</p>
      <h2>Configuration</h2><p>The power domain of MSMON_CSU is <span class="arm-defined-word">IMPLEMENTATION DEFINED</span>.
    </p><p>This register is present only when FEAT_MPAM is implemented, MPAMF_IDR.HAS_MSMON == 1 and MPAMF_MSMON_IDR.MSMON_CSU == 1. Otherwise, direct accesses to MSMON_CSU are <span class="arm-defined-word">RES0</span>.</p>
        <p>The power and reset domain of each MSC component is specific to that component.</p>
      <h2>Attributes</h2>
        <p>MSMON_CSU is a 32-bit register.</p>
      <h2>Field descriptions</h2><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="lr" colspan="1"><a href="#fieldset_0-31_31">NRDY</a></td><td class="lr" colspan="31"><a href="#fieldset_0-30_0">VALUE</a></td></tr></tbody></table><h4 id="fieldset_0-31_31">NRDY, bit [31]</h4><div class="field">
      <p>Not Ready. Indicates whether the monitor instance has possibly inaccurate data.</p>
    <table class="valuetable"><tr><th>NRDY</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>The monitor instance is ready and the MSMON_CSU.VALUE field is accurate.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>The monitor instance is not ready and the contents of the MSMON_CSU.VALUE field might be inaccurate or otherwise not represent the actual cache storage usage.</p>
        </td></tr></table></div><h4 id="fieldset_0-30_0">VALUE, bits [30:0]</h4><div class="field"><p>Cache storage usage measurement value if MSMON_CSU.NRDY is 0. Invalid if MSMON_CSU.NRDY is 1.</p>
<p>VALUE is the cache storage usage measured in bytes meeting the criteria set in <a href="ext-msmon_cfg_csu_flt.html">MSMON_CFG_CSU_FLT</a> and <a href="ext-msmon_cfg_csu_ctl.html">MSMON_CFG_CSU_CTL</a> for the monitor instance selected by <a href="ext-msmon_cfg_mon_sel.html">MSMON_CFG_MON_SEL</a>.</p></div><h2>Accessing MSMON_CSU</h2>
        <p>This register is within the MPAM feature page memory frames.</p>

      
        <p>In a system that supports Secure, Non-secure, Root, and Realm memory maps, there must be MPAM feature pages in all four address maps:</p>

      
        <ul>
<li>MSMON_CSU_s must only be accessible from the Secure MPAM feature page.
</li><li>MSMON_CSU_ns must only be accessible from the Non-secure MPAM feature page.
</li><li>MSMON_CSU_rt must only be accessible from the Root MPAM feature page.
</li><li>MSMON_CSU_rl must only be accessible from the Realm MPAM feature page.
</li></ul>

      
        <p>MSMON_CSU_s, MSMON_CSU_ns, MSMON_CSU_rt, and MSMON_CSU_rl must be separate registers:</p>

      
        <ul>
<li>The Secure instance (MSMON_CSU_s) accesses the cache storage usage monitor used for Secure PARTIDs.
</li><li>The Non-secure instance (MSMON_CSU_ns) accesses the cache storage usage monitor used for Non-secure PARTIDs.
</li><li>The Root instance (MSMON_CSU_rt) accesses the cache storage usage monitor used for Root PARTIDs.
</li><li>The Realm instance (MSMON_CSU_rl) accesses the cache storage usage monitor used for Realm PARTIDs.
</li></ul>

      
        <p>When RIS is implemented, reads and writes to MSMON_CSU access the cache storage usage monitor monitor instance for the cache resource instance selected by <a href="ext-msmon_cfg_mon_sel.html">MSMON_CFG_MON_SEL</a>.RIS and the cache storage usage monitor instance selected by <a href="ext-msmon_cfg_mon_sel.html">MSMON_CFG_MON_SEL</a>.MON_SEL.</p>

      
        <p>When RIS is not implemented, reads and writes to MSMON_CSU access the cache storage usage monitor monitor instance for the cache storage usage monitor instance selected by <a href="ext-msmon_cfg_mon_sel.html">MSMON_CFG_MON_SEL</a>.MON_SEL.</p>
      <h4>MSMON_CSU can be accessed through the memory-mapped interfaces:</h4><table class="info"><tr><th>Component</th><th>Frame</th><th>Offset</th><th>Instance</th></tr><tr><td>MPAM</td><td>MPAMF_BASE_s</td><td><span class="hexnumber">0x0840</span></td><td>MSMON_CSU_s</td></tr></table><p>This interface is accessible as follows:</p><ul><li>When MPAMF_CSUMON_IDR.CSU_RO == 0, accesses to this register are <span class="access_level">RW</span>.
          </li><li>When MPAMF_CSUMON_IDR.CSU_RO == 1, accesses to this register are <span class="access_level">RO</span>.
          </li></ul><table class="info"><tr><th>Component</th><th>Frame</th><th>Offset</th><th>Instance</th></tr><tr><td>MPAM</td><td>MPAMF_BASE_ns</td><td><span class="hexnumber">0x0840</span></td><td>MSMON_CSU_ns</td></tr></table><p>This interface is accessible as follows:</p><ul><li>When MPAMF_CSUMON_IDR.CSU_RO == 0, accesses to this register are <span class="access_level">RW</span>.
          </li><li>When MPAMF_CSUMON_IDR.CSU_RO == 1, accesses to this register are <span class="access_level">RO</span>.
          </li></ul><table class="info"><tr><th>Component</th><th>Frame</th><th>Offset</th><th>Instance</th></tr><tr><td>MPAM</td><td>MPAMF_BASE_rt</td><td><span class="hexnumber">0x0840</span></td><td>MSMON_CSU_rt</td></tr></table><p>This interface is accessible as follows:</p><ul><li>When FEAT_RME is implemented and MPAMF_CSUMON_IDR.CSU_RO == 0, accesses to this register are <span class="access_level">RW</span>.
          </li><li>When FEAT_RME is implemented and MPAMF_CSUMON_IDR.CSU_RO == 1, accesses to this register are <span class="access_level">RO</span>.
          </li></ul><table class="info"><tr><th>Component</th><th>Frame</th><th>Offset</th><th>Instance</th></tr><tr><td>MPAM</td><td>MPAMF_BASE_rl</td><td><span class="hexnumber">0x0840</span></td><td>MSMON_CSU_rl</td></tr></table><p>This interface is accessible as follows:</p><ul><li>When FEAT_RME is implemented and MPAMF_CSUMON_IDR.CSU_RO == 0, accesses to this register are <span class="access_level">RW</span>.
          </li><li>When FEAT_RME is implemented and MPAMF_CSUMON_IDR.CSU_RO == 1, accesses to this register are <span class="access_level">RO</span>.
          </li></ul><hr class="bottom_line"/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">30/03/2023 19:07; 997dd0cf3258cacf72aa7cf7a885f19a4758c3af</p><p class="copyconf">Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.</p></body>
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